Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM
Job Summary
Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
Matching Summary
Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
Skills & Requirements
Must-have
PCI Express controller verification
UVM methodology
SystemVerilog expertise
constrained random verification
IP/sub-system level verification
Nice-to-have
excellent PCIE protocol knowledge
system level architecture understanding
scripting and SW programming skills
good debugging and analytical skills
team player
Key Requirements
B.Tech./ M.Tech or equivalent experience
2+ years of relevant experience
Experience in verification at Unit/Sub-system/SOC level
Expertise in comprehensive verification of IP or interconnect protocols