Lead Design Verification Engineer

Intel Retiree Medical Plan Trust

Santa Clara, California, US
Base: $220,920.00-311,890.00 usd; bonus/equity: st...
End-to-end verification strategy
Chassis and interconnect ip programs
Protocol and memory subsystem knowledge
Define end-to-end verification strategy and execution for multiple critical chassis and interconnect IP programs from planning through signoff

Job Summary

  • Define end-to-end verification strategy and execution for multiple critical chassis and interconnect IP programs from planning through signoff.
  • Partner closely with architecture, design, software, and methodology teams to make early technical calls, unblock cross-team issues, and drive predictable high-quality delivery.
  • We offer a total compensation package that ranks among the best in the industry, consisting of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

Define end-to-end verification strategy and execution for multiple critical chassis and interconnect IP programs from planning through signoff.

Salary

Base: $220,920.00-311,890.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • End-to-end verification strategy
  • Chassis and interconnect IP programs
  • Protocol and memory subsystem knowledge
  • AI-assisted workflows
  • SystemVerilog/UVM, C/C++, Python
  • Simulation, formal, and emulation verification

Nice-to-have

  • Cross-team issue resolution
  • Mentoring and developing engineers
  • Adapt to evolving methodologies
  • Customer-driven end-to-end solutions

Key Requirements

  • 14+ years of relevant experience in design verification
  • BS/MS in Electrical Engineering, Computer Science, or related field
  • Proven deep expertise in interconnects, caches, and memory subsystems
  • Experience with AMBA CHI, ACE, AXI, PCIe, UCIe, and CXL
  • Demonstrated experience in verification of global functions
  • Strong background in simulation and formal verification methodologies
  • Advanced hands-on coding proficiency
  • Working familiarity with RTL, physical design constraints, and CAD tool flows
  • Demonstrated experience collaborating with formal verification and emulation teams

Work Rights

Not specified

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