Tfm And Ppa Physical Design Engineer

Intel Corporation

Bangalore, India
Hybrid
Backend physical design methodologies
Flow automation
Rtl2gds standard cell design
You will be responsible for Developing, debugging, and supporting tools, flows and methodologies covering backend physical design methodologies and flow automation for high performance blocks and full chip level using RTL2GDS standard cell level design techniques

Job Summary

  • You will be responsible for Developing, debugging, and supporting tools, flows and methodologies covering backend physical design methodologies and flow automation for high performance blocks and full chip level using RTL2GDS standard cell level design techniques.
  • Performing analysis of either synthesis, place-and-route, floor planning or signoff for static timing analysis on timing paths, formal equivalence verification, estimating power consumption, electrical rule checking, and circuit reliability to identify key issues.
  • Working with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low-power synthesizable CPU.

Matching Summary

You will be responsible for Developing, debugging, and supporting tools, flows and methodologies covering backend physical design methodologies and flow automation for high performance blocks and full chip level using RTL2GDS standard cell level design techniques.

Skills & Requirements

Must-have

  • backend physical design methodologies
  • flow automation
  • RTL2GDS standard cell design
  • static timing analysis
  • formal equivalence verification
  • power consumption estimation

Nice-to-have

  • highly motivated and knowledgeable teammates
  • strong verbal and written communication skills
  • building and enhancing tool capabilities

Key Requirements

  • Masters Degree in Electrical or Computer Engineering with 6+ years experience
  • Bachelor's Degree with 8+ years experience
  • Technical Expertise in Synthesis, Placement, CTS, Post-Route Optimization
  • P and R tools (CDNS and SNPS)
  • Familiarity with Verilog/ VHDL
  • Tcl, Perl, Python scripting

Work Rights

Not specified

Tailored Resume

Cover Letter