Soc Physical Design Timing Engineer

Intel Retiree Medical Plan Trust

Bangalore, India
Hybrid
Sta and timing closure expertise
Primetime tool experience
Tcl perl shell scripting skills
The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions

Job Summary

  • The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions.
  • This role requires hands-on experience with industry standard tools like Primetime and strong scripting skills in TCL, Perl, or Shell.
  • Candidates must possess a Bachelor's or Master's degree in Electrical/Electronics Engineering with over 10 years of relevant experience.

Matching Summary

The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions.

Skills & Requirements

Must-have

  • STA and timing closure expertise
  • Primetime tool experience
  • TCL Perl Shell scripting skills
  • SoC cycle understanding
  • Clock domain crossing debugging

Nice-to-have

  • Strong analytical problem solving skills
  • Self-motivated with initiative
  • Ability to work in diverse teams
  • Driving new methodologies

Key Requirements

  • Bachelor or Master of Engineering degree
  • 10+ years of Physical Implementation experience
  • Timing Closure expertise required

Work Rights

Not specified

Tailored Resume

Cover Letter