Sta Methodology Engineer

NXP

Bengaluru, India
10-12 years sta experience
Logic library benchmarking
Synthesis and pnr flows
The role involves benchmarking logic libraries across advanced technology nodes including 40nm down to 5nm using synthesis and PNR-based flows

Job Summary

  • The role involves benchmarking logic libraries across advanced technology nodes including 40nm down to 5nm using synthesis and PNR-based flows.
  • Candidates will collaborate with Timing Methodology and Signoff teams to ensure robust and efficient Static Timing Analysis methodologies.
  • Responsibilities include performing comprehensive STA, handling DRCs, annotation issues, and noise analysis within Logic Libraries Integration flows.

Matching Summary

The role involves benchmarking logic libraries across advanced technology nodes including 40nm down to 5nm using synthesis and PNR-based flows.

Skills & Requirements

Must-have

  • 10-12 years STA experience
  • Logic library benchmarking
  • Synthesis and PNR flows
  • Timing constraint validation
  • Multivoltage flow enablement

Nice-to-have

  • Python scripting proficiency
  • AI/GenAI understanding
  • Flow automation development
  • Strong collaboration skills
  • Proactive problem-solving approach

Key Requirements

  • Bachelor's or Master's in Electrical/Electronics Engineering
  • 10-12 years hands-on STA experience
  • Proven tape-out experience as block owner or lead
  • Deep understanding of SoC level timing closure

Work Rights

Not specified

Tailored Resume

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