Senior Asic Design Engineer, High Speed Io

NVIDIA

Not specified; not specified; comprehensive benefi...
Rtl design experience
High speed io protocols knowledge
Digital design fundamentals
The role involves owning the micro-architecture and RTL development for next-generation High Speed IO IP deployed in automotive chips

Job Summary

  • The role involves owning the micro-architecture and RTL development for next-generation High Speed IO IP deployed in automotive chips.
  • Candidates must possess strong digital design and verification fundamentals to drive timing closure and silicon validation.
  • NVIDIA offers a diverse, supportive environment where employees can make a lasting impact on the future of AI and computing.

Matching Summary

The role involves owning the micro-architecture and RTL development for next-generation High Speed IO IP deployed in automotive chips.

Salary

Not specified; Not specified; Comprehensive benefits package mentioned

Skills & Requirements

Must-have

  • RTL Design experience
  • High Speed IO protocols knowledge
  • Digital design fundamentals
  • Micro-architecture development
  • Timing closure skills
  • Silicon validation support

Nice-to-have

  • AI tool exposure like Claude
  • Cross-cultural collaboration skills
  • Strong problem solving abilities
  • Experience with CPU subsystems

Key Requirements

  • BTech/MTech in EE or ECE
  • 3+ years experience in complex unit design
  • Knowledge of HSIO standards and architectures

Work Rights

Not specified

Tailored Resume

Cover Letter