Principal Hls Engineer

Alcon

Goleta, CA, US
Base: $115,500.00 - $192,500.00; bonus/equity: not...
High level synthesis (hls)
Fpga logic design (vhdl, verilog)
Image processing pipeline development
Develop image processing pipelines on FPGA using High Level Synthesis (HLS) for next-gen surgical cameras

Job Summary

  • Develop image processing pipelines on FPGA using High Level Synthesis (HLS) for next-gen surgical cameras.
  • Design FPGA logic using VHDL and Verilog, interface with external hardware, and program embedded processors.
  • Join Alcon's mission to enhance sight and lives in a highly collaborative and diverse environment.

Matching Summary

Develop image processing pipelines on FPGA using High Level Synthesis (HLS) for next-gen surgical cameras.

Salary

Base: $115,500.00 - $192,500.00; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • High Level Synthesis (HLS)
  • FPGA logic design (VHDL, Verilog)
  • Image processing pipeline development
  • Embedded C programming
  • Agile Design Methodology
  • Version control (Git)

Nice-to-have

  • Object-oriented programming (C++)
  • Image sensor concepts
  • Image Signal Processor (ISP) knowledge
  • Schematics and PCB layout understanding
  • Electronic test equipment usage

Key Requirements

  • Bachelor’s Degree or Equivalent Experience
  • 5 Years of Relevant Experience
  • Fluent English communication

Work Rights

Not specified

Sponsorship: available

Tailored Resume

Cover Letter