Principal Engineer - Soc Clocking

Intel

Bangalore, India
Hybrid
15-20 years soc clocking experience
Pll dll architecture expertise
Transistor-level design and spice simulation
Lead the architecture and integration of SoC-wide clocking networks including generation, distribution, and domain crossing strategies

Job Summary

  • Lead the architecture and integration of SoC-wide clocking networks including generation, distribution, and domain crossing strategies.
  • Define and optimize power-performance-area trade-offs for complex clocking topologies while mentoring a team of designers.
  • Partner with foundries and EDA vendors to ensure robust silicon correlation and yield for high-reliability products.

Matching Summary

Lead the architecture and integration of SoC-wide clocking networks including generation, distribution, and domain crossing strategies.

Skills & Requirements

Must-have

  • 15-20 years SoC clocking experience
  • PLL DLL architecture expertise
  • Transistor-level design and Spice simulation
  • Clock tree synthesis and gating
  • Glitch-free clock domain crossing
  • RTL physical design verification collaboration

Nice-to-have

  • High-speed interface IP background
  • Server AI ML networking SoC experience
  • Silicon bring-up characterization debug
  • Patents or publications in circuit design
  • Power management custom memory design

Key Requirements

  • M.Tech B.Tech Ph.D. in Electrical Engineering
  • 15-20 years hands-on SoC clocking experience
  • Deep transistor-level design and Spice simulation skills
  • Experience leading multi-disciplinary global teams

Work Rights

Not specified

Tailored Resume

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