Front End Asic Rtl/logic Senior Design Engineer

Altera Digital Health

Penang, Malaysia
High speed digital design
Cutting edge technology node
Multi gigahz design
Responsible to lead, define & implement the design of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design

Job Summary

  • Responsible to lead, define & implement the design of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.
  • Work closely with verification team for design test plan and validation review and back-end team for floor planning, physical implementation, STA timing closure.
  • Work on post Silicon debug/characterization support of the designs.

Matching Summary

Responsible to lead, define & implement the design of high speed digital design in next generation IO in cutting edge technology node with multi GigaHz design.

Skills & Requirements

Must-have

  • high speed digital design
  • cutting edge technology node
  • multi GigaHz design
  • RTL coding using HDL
  • logic simulation and debug environments

Nice-to-have

  • strong communication skills
  • leadership skills
  • investigation skills
  • problem solving skills
  • analytical skills
  • scripting desirable

Key Requirements

  • minimum of 10 years ASIC frontend experience
  • BS/MS or PhD in Electronics Engineering
  • Knowledge of Spyglass
  • Knowledge of Synthesis
  • Knowledge of STA (PT)
  • Knowledge of UPF
  • Knowledge of UVM
  • Knowledge of Spice
  • Knowledge of DFT

Work Rights

Not specified

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