Performs functional verification of digital and mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements
Job Summary
Performs functional verification of digital and mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Matching Summary
Performs functional verification of digital and mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Skills & Requirements
Must-have
Verilog/System Verilog IP verification
UVM coding
DDR4/DDR5/LP5/LP6 protocol expertise
Low-power design using UPF
Simulation and debug experience
Checker development
Verification environment development
Nice-to-have
Analog behavioral modeling
Mentor junior engineers
Customer-driven solutions
Short development cycles
Key Requirements
BE/B.Tech with 12 years experience OR ME/M.Tech with 10 years experience
Experience in IP verification
Experience in UVM coding
Experience in System Verilog
Experience in DDR protocol verification
Experience in low-power design
Experience in multiple clock domain design
Experience in state machine design
Experience in simulation and debug
Experience in checker development
Experience in verification environment development