Drive physical layout implementation of memory building blocks within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies
Job Summary
Drive physical layout implementation of memory building blocks within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies.
Provide expert engineering judgment for critical decision-making and complex design trade-offs, including advanced IR drop analysis and mitigation, Reliability Verification (RV) analysis, ECO impact assessment, and project schedule optimization.
Mentor and guide junior layout engineers, providing technical guidance and knowledge transfer.
Matching Summary
Drive physical layout implementation of memory building blocks within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies.
Skills & Requirements
Must-have
Memory compiler layout design
Physical layout implementation
Cross-functional collaboration
Advanced CAD tool utilization
Methodology innovation and process refinement
Technical leadership and decision making
Nice-to-have
Mentoring junior engineers
Continuous improvement in layout efficiency
Strategic planning for future architectures
Cutting-edge memory technologies
Key Requirements
Bachelor's degree in Electronic/Microelectronic Engineering, Computer Engineering, or related
10+ years custom digital/analog layout design experience
Proficiency in Cadence Virtuoso, Synopsys Custom Compiler
Basic UNIX shell scripting, Tcl, Perl skills
Strong understanding of semiconductor fabrication processes and design rules
Experience with DRC/LVS/RV verification and debugging