Senior Digital Design Engineer, Ip And Methodology

Astera Labs

San Jose, United States
Base: $135,000 to $195,000; bonus/equity: eligible...
On-site
Rtl coding with systemverilog
Cpu subsystem design experience
Secure boot and cryptographic implementations
Astera Labs enables organizations to unlock the full potential of modern AI through purpose-built connectivity solutions

Job Summary

  • Astera Labs enables organizations to unlock the full potential of modern AI through purpose-built connectivity solutions.
  • The role involves owning the RTL implementation of complex digital designs from micro-architecture through sign-off.
  • Candidates will collaborate with verification, physical design, and DFT teams to deliver industry-leading products for data centers.

Matching Summary

Astera Labs enables organizations to unlock the full potential of modern AI through purpose-built connectivity solutions.

Salary

Base: $135,000 to $195,000; Bonus/Equity: Eligible for discretionary bonus and incentives; Benefits: Not specified

Skills & Requirements

Must-have

  • RTL coding with SystemVerilog
  • CPU subsystem design experience
  • Secure boot and cryptographic implementations
  • Clocking CDC and RDC methodologies
  • Python scripting in production

Nice-to-have

  • PCIe Gen 6/7 protocol familiarity
  • CMOS node experience below 7nm
  • UVM-based verification methodologies
  • Embedded firmware development exposure
  • RISC-V or ARM architecture integration

Key Requirements

  • Bachelor's degree in Electrical Engineering
  • 3+ years SoC/silicon product experience
  • Expertise in Synopsys or Cadence synthesis

Work Rights

Not specified

Tailored Resume

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