Principal Design Engineer

Cadence

Bangalore, India
5+ years analog ip design experience
Full cycle analog ip creation from spec to silicon
Hands-on design in plls and data converters
The role involves designing and leading high-speed IP development including USB3, PCIE, and DPHY

Job Summary

  • The role involves designing and leading high-speed IP development including USB3, PCIE, and DPHY.
  • Candidates must be strong individual contributors capable of participating in all aspects of development from analog design to silicon validation.
  • The position requires active participation in customer-facing discussions alongside technical execution.

Matching Summary

The role involves designing and leading high-speed IP development including USB3, PCIE, and DPHY.

Skills & Requirements

Must-have

  • 5+ years analog IP design experience
  • Full cycle analog IP creation from spec to silicon
  • Hands-on design in PLLs and data converters
  • Silicon debug and characterization participation

Nice-to-have

  • Customer facing discussion skills
  • Team player with good communication
  • PHY development experience in PCIE or USB

Key Requirements

  • B.Tech/BE/ME/Mtech degree required
  • Minimum 5 years of relevant experience
  • Experience with full analog IP lifecycle

Work Rights

Not specified

Tailored Resume

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