Base: $100k - $500k; bonus/equity: not specified; ...
On-site
Drc, lvs, erc, perc, antenna, dfm verification
Advanced node challenges (7nm, 5nm, 3nm)
Finfet design considerations
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes
Job Summary
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes.
You’ll lead physical verification closure, debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts.
We welcome candidates at various experience levels for this role and offer opportunities for leadership and mentoring in building scalable PV methodologies and automation.
Matching Summary
Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes.
Salary
Base: $100k - $500k; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
DRC, LVS, ERC, PERC, Antenna, DFM verification
advanced node challenges (7nm, 5nm, 3nm)
FinFET design considerations
Python, TCL scripting proficiency
ESD planning, padring integration
reliability analysis (IR drop, EM)
Nice-to-have
collaborative team player
mentor and technical leader
passion for AI
solving complex challenges
Key Requirements
BS or MS in Engineering
7–14 years of hands-on experience
CPU/IP/SoC physical verification expertise
Calibre, ICV, Pegasus, FC, Innovus tools
Eligibility to access U.S. export-controlled technology