Principal Firmware Engineer

Cadence

Austin, United States
Ddr5 jedec spec knowledge
Bare-metal firmware development
C programming for embedded
Be part of the Cadence DDR PHY IP Front End Design team responsible for developing firmware for DDR5 PHY using microcontrollers

Job Summary

  • Be part of the Cadence DDR PHY IP Front End Design team responsible for developing firmware for DDR5 PHY using microcontrollers.
  • Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.
  • Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations) and on Silicon bring-up boards.

Matching Summary

Be part of the Cadence DDR PHY IP Front End Design team responsible for developing firmware for DDR5 PHY using microcontrollers.

Skills & Requirements

Must-have

  • DDR5 JEDEC spec knowledge
  • bare-metal firmware development
  • C programming for embedded
  • firmware-hardware co-verification
  • RTL simulation debugging

Nice-to-have

  • innovators making an impact
  • solving what others can't

Key Requirements

  • Relevant experience in developing bare-metal firmware
  • Good Knowledge of C programming language
  • Good experience on Verification EDA Tools

Work Rights

Not specified

Tailored Resume

Cover Letter