Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM
Job Summary
Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
Matching Summary
Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
Skills & Requirements
Must-have
Pre-Silicon ASIC Verification
Formal Verification
UVM Verification
System Verilog
Python programming
EDA tools
Nice-to-have
AI-powered hardware verification
Team-oriented environment
Proactive problem solving
Continuous learning and innovation
Key Requirements
3-6 years of pre-silicon ASIC verification experience