Senior Soc Design Verification Engineer

Altera

Bengaluru, Karnataka, India
8+ years experience with complex asic designs
System verilog language proficiency
Uvm verification methodology expertise
The role involves creating test cases and test benches using UVM methodology for SoC architecture verification

Job Summary

  • The role involves creating test cases and test benches using UVM methodology for SoC architecture verification.
  • Candidates must coordinate cross-functional efforts with Design, SW, and Architecture teams to achieve full coverage verification plans.
  • Experience with emulation is considered an add-on skill for this pre-silicon system verification position.

Matching Summary

The role involves creating test cases and test benches using UVM methodology for SoC architecture verification.

Skills & Requirements

Must-have

  • 8+ years experience with complex ASIC designs
  • System Verilog language proficiency
  • UVM verification methodology expertise
  • Linux/Unix scripting skills
  • ARM based SoC verification experience

Nice-to-have

  • Emulation experience preferred
  • Design for Debug knowledge
  • Strong communication across geographies
  • Flexible in dynamic environment
  • Formal verification method experience

Key Requirements

  • 8+ years of experience with complex ASIC designs
  • Proficiency in System Verilog and UVM
  • Working knowledge of Perl or Python scripting

Work Rights

Not specified

Tailored Resume

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