Substrate / Advanced Package Engineer (7103)

TSMC

San Jose, CA, United States
Base: $153,500 to $250,000 py; bonus/equity: not s...
Advanced packaging technologies
Substrate design
Warpage and thermal modeling
Support TSMC’s leadership in 3DIC and advanced packaging by extending expertise beyond chip-level design into package-level integration

Job Summary

  • Support TSMC’s leadership in 3DIC and advanced packaging by extending expertise beyond chip-level design into package-level integration.
  • Collaborate with cross-functional teams to define specifications and requirements for next-generation 3DIC applications.
  • Work on industry-defining projects with world-class engineers and shape the future of system integration.

Matching Summary

Support TSMC’s leadership in 3DIC and advanced packaging by extending expertise beyond chip-level design into package-level integration.

Salary

Base: $153,500 to $250,000 per year; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • Advanced packaging technologies
  • Substrate design
  • Warpage and thermal modeling
  • EDA tools
  • 3DIC design
  • High-speed I/O integration

Nice-to-have

  • Machine learning for design optimization
  • Reliability analysis
  • Multi-physics analysis

Key Requirements

  • Master’s degree or Ph.D. in Electrical Engineering, Mechanical Engineering, or related field
  • 15+ years of hands-on expertise in advanced packaging technologies
  • Understanding of semiconductor device physics and packaging process technologies
  • Proven ability to drive solutions in ambiguous, research-oriented contexts

Work Rights

Must have US citizenship

Tailored Resume

Cover Letter