Principal Verification Lead Engineer

Cadence

Austin, Texas, United States
Systemverilog assertions (sva)
Uvm environment development
Processor integration experience
The role focuses on leading a team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks

Job Summary

  • The role focuses on leading a team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.
  • Candidates must develop complex functional coverage models and automated regression environments using tools like Jenkins and Cadence vManager.
  • This position requires strong technical execution skills to debug complex RTL failures and coordinate with design engineers.

Matching Summary

The role focuses on leading a team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.

Skills & Requirements

Must-have

  • SystemVerilog Assertions (SVA)
  • UVM environment development
  • Processor integration experience
  • Regression management automation
  • Scripting in Python or Tcl

Nice-to-have

  • Multi-protocol interface knowledge
  • Microarchitectural bug resolution
  • Technical leadership skills
  • Project planning expertise

Key Requirements

  • B.S/M.S in EEE
  • 6+ years VLSI verification experience
  • Experience with RISC-V or ARM processors

Work Rights

Not specified

Tailored Resume

Cover Letter