Dft Rtl Design And Integration Engineer

Intel

Petah-Tikva, Israel
Hybrid
Register transfer level (rtl) coding
Design-for-test (dft) methodologies
Scan insertion and related flows
The role involves developing logic design, RTL coding, and providing DFT timing closure support for complex SoC architectures

Job Summary

  • The role involves developing logic design, RTL coding, and providing DFT timing closure support for complex SoC architectures.
  • Candidates will define and implement SoC main debug fabrics such as TAP and Scan while working closely with architecture and manufacturing teams.
  • The position requires driving coverage improvement, reducing DPM, and enabling content on both pre-silicon environments and real silicon.

Matching Summary

The role involves developing logic design, RTL coding, and providing DFT timing closure support for complex SoC architectures.

Skills & Requirements

Must-have

  • Register Transfer Level (RTL) coding
  • Design-for-Test (DFT) methodologies
  • Scan insertion and related flows
  • Linux environment proficiency

Nice-to-have

  • Automatic tool development experience
  • Collaboration with Architecture teams
  • Silicon validation support skills

Key Requirements

  • Bachelor's degree in Electrical Engineering or related field
  • 5+ years of experience in Design-for-Test (DFT) methodologies
  • 2+ years of hands-on experience with Scan insertion

Work Rights

Not specified

Tailored Resume

Cover Letter