Synthesis & Front-end Implementation Engineer

NXP USA INC.

Synopsys design compiler proficiency
Static timing analysis (sta) expertise
Verilog/system verilog digital design
This role is crucial for translating RTL designs into optimized gate-level netlists while meeting performance, power, and area targets

Job Summary

  • This role is crucial for translating RTL designs into optimized gate-level netlists while meeting performance, power, and area targets.
  • The engineer will perform synthesis, conduct static timing analysis, and execute formal verification to ensure functional equivalency.
  • Candidates must possess strong problem-solving skills and the ability to collaborate effectively with RTL designers and physical design engineers.

Matching Summary

This role is crucial for translating RTL designs into optimized gate-level netlists while meeting performance, power, and area targets.

Skills & Requirements

Must-have

  • Synopsys Design Compiler proficiency
  • Static Timing Analysis (STA) expertise
  • Verilog/System Verilog digital design
  • Formal verification (LEC) experience
  • Low-power design techniques understanding
  • Tcl Python Perl scripting skills

Nice-to-have

  • Design for Testability (DFT) principles
  • Collaboration across multiple time zones
  • CAD tool integration experience
  • Hierarchical synthesis methodologies

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 2+ years of experience in digital ASIC/SoC design
  • Proficiency with Synopsys PrimeTime and Formality tools

Work Rights

Not specified

Tailored Resume

Cover Letter