Base: $225,000 to $250,000 annually; bonus/equity:...
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15+ years asic/soc verification experience
3+ years managerial leadership role
Expertise in arm architecture and amba protocols
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Alphawave IP is seeking a Design Verification Manager to lead verification efforts for advanced ARM multi-core CPU designs. The ideal candidate will have extensive experience in ASIC verification and proven leadership skills, with a focus on pre-silicon validation and collaboration with cross-functional teams.
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Job Summary
The role involves leading a team to verify complex ARM-based SoC designs for mission-critical data communication applications.
Candidates will define verification strategies, drive pre-silicon validation, and collaborate with cross-functional teams including design and software.
The company offers competitive compensation ranging from $225,000 to $250,000 annually along with comprehensive health and wellness benefits.
Matching Summary
Match Score: 75
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Alphawave IP is seeking a Design Verification Manager to lead verification efforts for advanced ARM multi-core CPU designs. The ideal candidate will have extensive experience in ASIC verification and proven leadership skills, with a focus on pre-silicon validation and collaboration with cross-functional teams.
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Salary
Base: $225,000 to $250,000 annually; Bonus/Equity: Short-term incentive program and ESPP participation; Benefits: Comprehensive health plans, WSA, EAP, and flexible time off
Skills & Requirements
Must-have
15+ years ASIC/SoC verification experience
3+ years managerial leadership role
Expertise in ARM architecture and AMBA protocols
Strong hands-on UVM and SystemVerilog skills
Experience with C/C++ or Python scripting
Nice-to-have
Experience with Emulation and FPGA prototyping
Knowledge of Cache coherency protocols
Familiarity with post-silicon validation processes
Prior tapeout-focused environment experience
Background in high-performance computing verification
Key Requirements
Bachelor's or Master's degree in Electrical Engineering
15+ years total experience in ASIC/SoC verification