Asic Engineering Technical Leader

Cisco

San Jose, CA, US
Base: $191,400.00 to $281,400.00; bonus/equity: gr...
On-site
10+ years asic hardware development experience
Jtag protocols scan and bist architectures
Post-silicon test bring up and debug
You will be the lead to drive the DFT/DFx and quality process through the early product life cycle including architecture definitions and RTL implementation

Job Summary

  • You will be the lead to drive the DFT/DFx and quality process through the early product life cycle including architecture definitions and RTL implementation.
  • The role involves leading a team of engineers to deliver expected implementations on schedule while developing comprehensive Design-for-Test solutions.
  • Cisco offers competitive compensation ranging from $191,400 to $281,400 plus benefits like medical insurance, 401(k) matching, and flexible vacation time.

Matching Summary

You will be the lead to drive the DFT/DFx and quality process through the early product life cycle including architecture definitions and RTL implementation.

Salary

Base: $191,400.00 to $281,400.00; Bonus/Equity: Grants of Cisco restricted stock units eligible; Benefits: Medical, dental, vision, 401(k) match, paid parental leave

Skills & Requirements

Must-have

  • 10+ years ASIC hardware development experience
  • Jtag protocols Scan and BIST architectures
  • Post-silicon test bring up and debug
  • RTL QA checks lint and CDC
  • Drive DFT quality process early product life cycle

Nice-to-have

  • Scripting skills Tcl Python Perl
  • Experience with bare die stacked die models
  • Innovative Hardware DFT test strategy aspects
  • Cross-functional solution brainstorming leadership

Key Requirements

  • Bachelor's or Master's Degree in Electrical or Computer Engineering
  • 10+ years of ASIC Hardware Development experience
  • Prior experience on hardware design specifications and verification plan/matrix

Work Rights

Not specified

Tailored Resume

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