Senior Asic Engineer

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3+ years of relevant work experience
Strong communication skills
Front-end asic design foundation
The PMU and SECIP team is responsible for critical GPU IPs including PMU, GSP, and SEC

Job Summary

  • The PMU and SECIP team is responsible for critical GPU IPs including PMU, GSP, and SEC.
  • The role involves analyzing architectural requirements and developing wrapper logic for integration.
  • Collaboration with multiple teams is essential to ensure system-level performance meets firmware requirements.

Matching Summary

The PMU and SECIP team is responsible for critical GPU IPs including PMU, GSP, and SEC.

Skills & Requirements

Must-have

  • 3+ years of relevant work experience
  • strong communication skills
  • front-end ASIC design foundation

Nice-to-have

  • experience in system-level chip integration
  • familiarity with RISC-V processor subsystems
  • exposure to multi-die architectures

Key Requirements

  • BS or MS in Electrical Engineering or Computer Engineering
  • MS preferred

Work Rights

Not specified

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