Design Verification Lead Engineer

Cadence

Austin, United States
Systemverilog assertions (sva)
Constraint randomization
Uvm
The Lead DV Engineer focuses on the execution and technical management of verification projects

Job Summary

  • The Lead DV Engineer focuses on the execution and technical management of verification projects.
  • You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.
  • We’re doing work that matters. Help us solve what others can’t.

Matching Summary

The Lead DV Engineer focuses on the execution and technical management of verification projects.

Skills & Requirements

Must-have

  • SystemVerilog Assertions (SVA)
  • constraint randomization
  • UVM
  • processor integration
  • AMBA/PCIe protocols
  • scripting for automation

Nice-to-have

  • technical alignment
  • project planning
  • progress tracking

Key Requirements

  • 5-8+ years of experience in VLSI design verification
  • B.S/M.S in EEE
  • Experience with RISC-V or ARM processors
  • Experience with AMBA/PCIe protocols
  • Expertise in Perl, Python, or Tcl scripting

Work Rights

Not specified

Tailored Resume

Cover Letter