Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Job Summary
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
Responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Skills & Requirements
Must-have
Hardware Design-for-Test (DFT) features
DFT IP development
JTAG protocols, Scan insertion, ATPG
ATPG and EDA tools (TestMax, Tetramax, Tessent)
Gate level simulation, debugging with VCS
Post-silicon validation and debug
ATE patterns, P1687
Nice-to-have
Innovative DFT trends
Collaborative multi-functional teams
Thrive in multifaceted environment
Test Static Timing Analysis
Scripting skills: Tcl, Python/Perl
Key Requirements
4-8 years related work experience
Bachelor's or Master’s Degree in Electrical or Computer Engineering
4-6 years of experience with degree
Ability to craft solutions and debug with minimal mentorship