Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications
Job Summary
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Explore AI/ML-driven solutions for coverage analysis, bug triage, and productivity improvements.
Matching Summary
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Skills & Requirements
Must-have
System Verilog/UVM based testbench
constrained-random stimulus
coverage closure
regression infrastructure management
Pre-Silicon validation
advanced computer architecture
Nice-to-have
AI/ML-driven solutions
formal verification adoption
emulation techniques
automation techniques
innovation in verification processes
Key Requirements
7+ years of experience
Bachelor's degree plus 7+ years
Master's degree plus 6+ years
PhD plus 5+ years
Verilog, System Verilog, UVM, and Python programming skills