Senior Verification Engineer

Indclutch

Jerusalem, Israel
On-site
Systemverilog/uvm verification environments
Constrained-random and coverage-driven verification
Python scripting for verification automation
Indclutch is seeking a Senior Verification Engineer to join their Design Verification team in Jerusalem, Haifa, or Tel Aviv. The role involves verifying high-speed SerDes IP and requires expertise in SystemVerilog, UVM, and Python, focusing on digital design and collaboration with various teams

Job Summary

  • Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP.
  • Develop and maintain advanced SystemVerilog/UVM verification environments.
  • Leverage AI-assisted tools as a core part of your daily engineering workflow.

Matching Summary

Match Score: 85

Indclutch is seeking a Senior Verification Engineer to join their Design Verification team in Jerusalem, Haifa, or Tel Aviv. The role involves verifying high-speed SerDes IP and requires expertise in SystemVerilog, UVM, and Python, focusing on digital design and collaboration with various teams.

Skills & Requirements

Must-have

  • SystemVerilog/UVM verification environments
  • constrained-random and coverage-driven verification
  • Python scripting for verification automation
  • FW/HW joint verification flows
  • AI-assisted tools in workflow

Nice-to-have

  • mixed-signal or analog IP verification
  • formal verification tools
  • high-speed protocols (PCIe, Ethernet)
  • DSP algorithm verification
  • AI-assisted engineering tools experience

Key Requirements

  • 4–7 years of hands-on experience
  • Bachelor's or Master's degree
  • independent contribution to verification sign-off

Work Rights

Not specified

Tailored Resume

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