This role serves as the technical authority defining the overarching strategy for Design for Test and Debug across next-generation FPGA and SoC families
Job Summary
This role serves as the technical authority defining the overarching strategy for Design for Test and Debug across next-generation FPGA and SoC families.
The successful candidate will drive the adoption of advanced DFX features like IEEE 1687 and 1838 while optimizing test data volume and application time.
You will partner with global teams to ensure DFT requirements are baked into hardware specifications and influence EDA vendor roadmaps to align with Altera's needs.
Matching Summary
This role serves as the technical authority defining the overarching strategy for Design for Test and Debug across next-generation FPGA and SoC families.
Skills & Requirements
Must-have
10-12 years DFT/DFD experience
Hierarchical DFT and Scan Compression
IEEE 1687 IJTAG and 1838 standards
Multi-die chiplet architecture knowledge
Silicon bring-up and failure analysis
Tessent or Synopsys DFT tool expertise
Nice-to-have
FPGA configuration RAM testing experience
ASIL-D functional safety design background
Mentoring senior engineering staff
Strategic stakeholder management skills
Python/Tcl scripting proficiency
Key Requirements
BS/MS/Ph.D. in Electrical or Computer Engineering
Minimum 10-12 years hands-on DFT/DFD experience
At least 4 years in an architectural or lead capacity
Deep familiarity with semiconductor end-to-end product life cycle