Senior Design Verification Engineer- Mixed Signal Ip

Intel Corporation

Folsom, California, US
$164,470.00-311,890.00 usd; not specified; health,...
Hybrid
Mixed signal logic verification
Analog behavioral modeling
Ip verification plans
Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements

Job Summary

  • Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
  • Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.

Salary

$164,470.00-311,890.00 USD; Not specified; health, retirement, and vacation

Skills & Requirements

Must-have

  • Mixed signal logic verification
  • Analog behavioral modeling
  • IP verification plans
  • Test benches
  • Verification environment
  • System simulation models
  • Root cause analysis
  • Functional verification infrastructure

Nice-to-have

  • DDRPHY validation
  • DFI/DDR/LPDDR protocols
  • Python/Perl scripting
  • Formal Property Verification
  • Git/Perforce/CVS

Key Requirements

  • BS degree + 8+ years experience
  • MS degree + 6+ years experience
  • PhD + 4+ years experience
  • System Verilog
  • OVM/UVM
  • Validation flow
  • Waveform debug
  • Functional coverage
  • Code coverage
  • VCS NLP and non-NLP simulations
  • GLS

Work Rights

Not specified

Tailored Resume

Cover Letter