Senior Verification Engineer - Hsio Unit Level

NVIDIA

Hybrid
Uvm methodology experience
High speed io verification
Systemverilog development
This role involves architecting testbenches and crafting verification environments using SystemVerilog and UVM methodology for complex automotive chips

Job Summary

  • This role involves architecting testbenches and crafting verification environments using SystemVerilog and UVM methodology for complex automotive chips.
  • Candidates will work with architects, designers, FPGA, and post-silicon teams to ensure robust unit verification for high-performance CPU and memory subsystems.
  • NVIDIA offers a diverse, supportive environment where employees are inspired to do their best work on the future of AI and computing.

Matching Summary

This role involves architecting testbenches and crafting verification environments using SystemVerilog and UVM methodology for complex automotive chips.

Skills & Requirements

Must-have

  • UVM methodology experience
  • High Speed IO verification
  • SystemVerilog development
  • USB UFS MPPHY Ethernet verification
  • Functional coverage implementation

Nice-to-have

  • AI code development exposure
  • Formal verification knowledge
  • Automation mindset
  • Cross-cultural collaboration skills

Key Requirements

  • BTech or MTech in ECE, EE, CSE
  • 4+ years verification closure experience
  • Experience with 10G/1G Ethernet MAC

Work Rights

Not specified

Tailored Resume

Cover Letter