Senior Asic Verification Engineer

Cisco UK

System verilog proficiency
Uvm methodology experience
Design verification background
The role involves developing and upgrading test benches for the Silicon One family of complex ASIC chips used in global switching systems

Job Summary

  • The role involves developing and upgrading test benches for the Silicon One family of complex ASIC chips used in global switching systems.
  • Engineers will collaborate with design and hardware teams to perform end-to-end verification across simulation, emulation, and ASIC bring-up phases.
  • Candidates must have at least eight years of experience in Design Verification with a degree in Electrical or Computer engineering.

Matching Summary

The role involves developing and upgrading test benches for the Silicon One family of complex ASIC chips used in global switching systems.

Skills & Requirements

Must-have

  • System Verilog proficiency
  • UVM methodology experience
  • Design Verification background
  • Constrained random design environments
  • Python Perl shell scripting

Nice-to-have

  • C++ programming knowledge
  • Formal Verification experience
  • Emulation testing familiarity
  • Perforce Git database tools
  • Cross-block verification skills

Key Requirements

  • 8+ years Design Verification experience
  • Degree in Electrical or Computer Engineering
  • Proficiency in System Verilog and UVM

Work Rights

Not specified

Tailored Resume

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