Physical Design Engineering Manager

Intel

Austin, Texas, US
Base: $164,470.00-311,890.00 usd; bonus/equity: st...
Rtl to gds flow management
Soc physical design verification
Clock tree synthesis expertise
The role involves leading a passionate team of engineers responsible for delivering cutting-edge semiconductor designs from RTL to GDS

Job Summary

  • The role involves leading a passionate team of engineers responsible for delivering cutting-edge semiconductor designs from RTL to GDS.
  • Candidates must provide technical guidance on complex processes including clock tree synthesis, place-and-route, and power delivery optimization.
  • Intel offers a competitive total compensation package including stock bonuses, health benefits, and retirement programs.

Matching Summary

The role involves leading a passionate team of engineers responsible for delivering cutting-edge semiconductor designs from RTL to GDS.

Salary

Base: $164,470.00-311,890.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation programs

Skills & Requirements

Must-have

  • RTL to GDS flow management
  • SoC physical design verification
  • Clock tree synthesis expertise
  • Place-and-route optimization
  • Power delivery architecture
  • Team leadership and performance management

Nice-to-have

  • Innovation in semiconductor design
  • Fostering team engagement
  • Continuous improvement mindset
  • Cross-functional collaboration skills

Key Requirements

  • Bachelor's degree with 6 years experience or Master's with 4 years
  • Experience managing SoC physical design verification flows
  • Proven track record in resolving design violations at block and chip levels

Work Rights

Not specified

Tailored Resume

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