Job Summary

• Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division working on next generation Artificial Intelligence and PCIe Switch Products.
• This position involves ownership of chip floor planning, partition creation, clock tree and delivery of top level partitions, as well as managing cross functional interactions with package teams.
• Broadcom offers a competitive and comprehensive benefits package including medical, dental, vision, 401(K) with company matching, ESPP, paid holidays, sick leave, and vacation time.

Matching Summary

Salary

Base: $120,000 - $192,000; Bonus/Equity: discretionary annual bonus and equity awards; Benefits: medical, dental, vision, 401(K) matching, ESPP, paid leave

Skills & Requirements

Key Requirements

• Bachelor's degree and 8+ years experience or Master's degree and 6+ years experience
• experience resolving chip level DRC/LVS/EMIR issues
• tape out experience for advanced nodes
• must work in person at San Jose site

Work Rights