Senior Fpga Compiler (router) Engineer

Altera

San Jose, California, United States
Base: $187.0k - $270.7k usd; bonus/equity: incenti...
9+ years fpga/asic design tools experience
Strong graph algorithms and data structures expertise
Proficiency in c/c++ software development
This role focuses on designing and optimizing FPGA routing algorithms to directly impact device performance, power, and usability

Job Summary

  • This role focuses on designing and optimizing FPGA routing algorithms to directly impact device performance, power, and usability.
  • Candidates will collaborate cross-functionally with architecture, synthesis, and hardware teams to align routing strategies with device capabilities.
  • The position offers the opportunity to solve complex algorithmic challenges at scale while working on core compiler technology for next-generation FPGA platforms.

Matching Summary

This role focuses on designing and optimizing FPGA routing algorithms to directly impact device performance, power, and usability.

Salary

Base: $187.0K - $270.7K USD; Bonus/Equity: Incentive opportunities available based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • 9+ years FPGA/ASIC design tools experience
  • Strong graph algorithms and data structures expertise
  • Proficiency in C/C++ software development
  • Experience with placement, routing, and timing closure flows
  • Knowledge of maze routing and negotiated congestion algorithms

Nice-to-have

  • Experience with Quartus or Vivado commercial toolchains
  • Familiarity with parallel/distributed computing for EDA
  • Background in timing analysis or placement algorithms
  • Scripting skills in Python or Tcl for automation

Key Requirements

  • Bachelor's or Master's degree in EE, CE, or CS
  • 9+ years of experience in EDA or related fields
  • Eligibility for required U.S. export authorizations

Work Rights

Must be eligible for U.S. export authorizations

Tailored Resume

Cover Letter