Base: $175,000 to $275,000 annually; bonus/equity:...
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Rtl design and integration
High-performance, power-efficient solutions
External asic vendor management
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Cerebras Systems is seeking a Lead RTL Design Engineer to join their Sunnyvale, CA team, focusing on high-performance, power-efficient chip design for their innovative wafer-scale AI architecture. The ideal candidate will have extensive experience in RTL design, integration, and collaboration with external vendors.
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Job Summary
As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).
Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
Collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production.
Matching Summary
Match Score: 75
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Cerebras Systems is seeking a Lead RTL Design Engineer to join their Sunnyvale, CA team, focusing on high-performance, power-efficient chip design for their innovative wafer-scale AI architecture. The ideal candidate will have extensive experience in RTL design, integration, and collaboration with external vendors.
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Salary
Base: $175,000 to $275,000 annually; Bonus/Equity: included; Benefits: Not specified
Skills & Requirements
Must-have
RTL design and integration
High-performance, power-efficient solutions
External ASIC vendor management
Networking stack experience
PCIe, CPU interfaces, Serdes technology
Nice-to-have
FPGA development toolchain experience
Key Requirements
Master’s degree in Computer Science, Electrical Engineering, or equivalent
8-15 years of experience in delivering complex, high performance high quality RTL designs
Experience with Front End Chip integration and third-party IP integration
Experience collaborating and managing external vendors
Working knowledge of scripting tools : Python, TCL