Staff Design Verification Engineer Category Location Toronto, Ontario

Talentlab Inc

Toronto, Ontario, Canada
On-site
High-speed mixed-signal phys
Scalable uvm testbench components
Systemverilog and uvm proficiency
Architect, design, and verify DSPs using high-speed mixed-signal PHYs such as PCIe and Ethernet

Job Summary

  • Architect, design, and verify DSPs using high-speed mixed-signal PHYs such as PCIe and Ethernet.
  • Build scalable UVM testbench components for verifying complex RTL and firmware functionality.
  • Own the full verification lifecycle—from creating and reviewing verification plans to implementation and sign-off for tape-out.

Matching Summary

Architect, design, and verify DSPs using high-speed mixed-signal PHYs such as PCIe and Ethernet.

Skills & Requirements

Must-have

  • high-speed mixed-signal PHYs
  • scalable UVM testbench components
  • SystemVerilog and UVM proficiency
  • full verification lifecycle ownership

Nice-to-have

  • SerDes and DSP cores understanding
  • protocol development across new variants
  • collaboration with design team
  • mentoring junior engineers

Key Requirements

  • Minimum of 9 years of ASIC design verification experience
  • Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or related
  • Strong hands-on testbench building and debugging expertise
  • Familiarity with leading EDA tools and methodologies

Work Rights

Not specified

Tailored Resume

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