Senior Soc Physical Design/power Analysis/rdl Engineer

Altera Digital Health

San Jose, California, United States
Base: $127,400 - $184,400 usd; bonus/equity: incen...
Physical design implementation experience
Bump/rdl/mimcap planning expertise
Sta lec erc drc signoff flows
The role involves performing physical design implementation and power integrity analysis for SoC blocks and subsystems

Job Summary

  • The role involves performing physical design implementation and power integrity analysis for SoC blocks and subsystems.
  • Candidates must possess extensive hands-on experience with physical design signoff flows including STA, LEC, ERC, and DRC.
  • The position requires multiple tape-out experiences in deep submicron process nodes and expertise in BUMP/RDL/MIMCAP planning.

Matching Summary

The role involves performing physical design implementation and power integrity analysis for SoC blocks and subsystems.

Salary

Base: $127,400 - $184,400 USD; Bonus/Equity: Incentive opportunities available based on performance; Benefits: Not specified

Skills & Requirements

Must-have

  • Physical design implementation experience
  • BUMP/RDL/MIMCAP planning expertise
  • STA LEC ERC DRC signoff flows
  • Perl TCL Python scripting skills
  • Deep submicron process tape-out experience

Nice-to-have

  • Low power design methodologies
  • Mentoring junior team members
  • Flow automation development
  • Design optimization for power and frequency

Key Requirements

  • Bachelor's degree in computer or electronic engineering
  • 5+ years of relevant physical design experience
  • Multiple tape-out experience in deep submicron nodes
  • Hands-on expertise with Perl, TCL, Python, VHDL, and Verilog

Work Rights

Not specified

Tailored Resume

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