Principal Design Verification Engineer

GlobalFoundries

$153,000.00 - $265,000.00 py
Systemverilog
Uvm-based environments
Constrained random verification
The successful candidate will work on verification of processor components, focusing on CPU core functionality, coherency, and cache subsystems

Job Summary

  • The successful candidate will work on verification of processor components, focusing on CPU core functionality, coherency, and cache subsystems.
  • This role offers an excellent opportunity to gain hands-on experience with advanced verification methodologies and collaborate with world-class architects and designers.
  • GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential.

Matching Summary

The successful candidate will work on verification of processor components, focusing on CPU core functionality, coherency, and cache subsystems.

Salary

$153,000.00 - $265,000.00

Skills & Requirements

Must-have

  • SystemVerilog
  • UVM-based environments
  • constrained random verification
  • CPU architectures
  • cache and coherency concepts
  • scripting languages

Nice-to-have

  • RISC-V architecture exposure
  • interconnect protocols knowledge
  • FPGA prototyping experience

Key Requirements

  • 8+ years of experience
  • Bachelor's degree in Engineering
  • SystemVerilog, UVM, constrained random verification
  • CPU or SoC verification experience
  • RISC-V, ARM, or MIPS familiarity
  • Python, Perl, or Shell scripting skills

Work Rights

Not specified

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