Principal Engineer, Design Technology Co-optimization

Intel Jobs

Hillsboro, Oregon, US
$220,920.00-311,890.00 usd; bonus/equity: stock bo...
Hybrid
Advanced semiconductor technology
Foundation ip design
Standard cell library design
As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs

Job Summary

  • As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.
  • Your responsibility includes optimizing library circuits in close collaboration with physical design engineers to provide optimally tuned layout to improve cell performance, power and area.
  • We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

As a logic library vertical lead, you will be responsible for driving optimization of standard cell libraries on Intel's leading edge process nodes to meet internal and external foundry customer needs.

Salary

$220,920.00-311,890.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • advanced semiconductor technology
  • foundation IP design
  • standard cell library design
  • library cell characterization
  • semiconductor foundry ecosystem

Nice-to-have

  • collaborative mindset
  • technical leadership
  • product designs
  • signoff methodology
  • pre and post Si benchmarking

Key Requirements

  • 10+ years of industry experience
  • Ph.D. or master's degree
  • Experience with library cell characterization methodology and tools
  • Experience with Spice circuit simulations
  • Excellent oral and written communication skills

Work Rights

Not specified

Tailored Resume

Cover Letter