Silicon Packaging Design Engineer

Intel

Phoenix, Arizona, United States
Base: $105,650.00-149,150.00 usd; bonus/equity: st...
Microelectronic package or pcb physical layout design
Package design tools siemens xpedition cadence allegro
Physical layout aspects of substrate design custom layouts
You will play a pivotal role in driving the development of advanced substrate designs from concept through tape-out

Job Summary

  • You will play a pivotal role in driving the development of advanced substrate designs from concept through tape-out.
  • The position offers an exciting opportunity to work collaboratively with silicon and hardware teams to deliver world-class solutions.
  • Intel offers a total compensation package that includes competitive pay, stock bonuses, and comprehensive benefit programs.

Matching Summary

You will play a pivotal role in driving the development of advanced substrate designs from concept through tape-out.

Salary

Base: $105,650.00-149,150.00 USD; Bonus/Equity: Stock bonuses included; Benefits: Health, retirement, and vacation

Skills & Requirements

Must-have

  • Microelectronic package or PCB physical layout design
  • Package design tools Siemens Xpedition Cadence Allegro
  • Physical layout aspects of substrate design custom layouts
  • Electrical Engineering Mechanical Engineering Material Sciences degree

Nice-to-have

  • Experience with package I/O routing and technology development
  • Familiarity with electrical modeling tools PowerDC HyperLynx Q3D HFSS
  • Strong analytical ability and problem-solving skills debugging
  • Experience with Package Layout Automation PLA and FIELD tools
  • Scripting experience using Python VB C languages

Key Requirements

  • Bachelor's degree with 1+ years experience OR Master's with 6 months experience
  • 6+ months experience with microelectronic package or PCB physical layout design
  • Familiarity with package design tools like Siemens Xpedition or Cadence Allegro

Work Rights

Not specified

Tailored Resume

Cover Letter