Lead Principal Engineer, Layout Design

Micron Technology

7+ years semiconductor industry experience
Cadence virtuoso custom ic layout expertise
Dram sub-system physical implementation
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence

Job Summary

  • Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.
  • The role involves ownership of the physical implementation of DRAM and mixed-signal circuits, translating schematics into robust, manufacturable layouts.
  • Candidates must drive layout-dependent performance improvements in area, timing, power, and yield while supporting silicon validation and tapeout readiness.

Matching Summary

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence.

Skills & Requirements

Must-have

  • 7+ years semiconductor industry experience
  • Cadence Virtuoso custom IC layout expertise
  • DRAM sub-system physical implementation
  • Calibre Assura PVS physical verification
  • Hierarchical block and top-level floorplanning
  • DRC LVS PEX signoff closure management
  • EM IR antenna ESD reliability checks

Nice-to-have

  • SKILL TCL Python Perl scripting automation
  • Master's degree or PhD in EE/CE
  • Advanced-node DFM and patterning knowledge
  • Silicon validation and debug collaboration
  • Cross-team technical leadership skills
  • Memory array timing optimization experience

Key Requirements

  • Bachelor's degree in Electrical Engineering or equivalent
  • 7+ years of experience in Semiconductor industry
  • Proven track record delivering DRAM tapeouts

Work Rights

Not specified

Tailored Resume

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