Bachelor's or master's degree in electrical or computer engineering
1-4 years of experience in dft and silicon engineering
Experience with jtag protocols, scan, and bist architectures
The role involves implementing Hardware Design-for-Test (DFT) features to support ATE, in-system test, and diagnostics for Cisco's core networking products
Job Summary
The role involves implementing Hardware Design-for-Test (DFT) features to support ATE, in-system test, and diagnostics for Cisco's core networking products.
Candidates will collaborate with multi-functional teams to develop innovative DFT IP and play a key role in full chip design integration.
The team drives reusable test and debug strategies for new silicon device models including bare die and stacked die configurations.
Matching Summary
The role involves implementing Hardware Design-for-Test (DFT) features to support ATE, in-system test, and diagnostics for Cisco's core networking products.
Skills & Requirements
Must-have
Bachelor's or Master's Degree in Electrical or Computer Engineering
1-4 years of experience in DFT and silicon engineering
Experience with Jtag protocols, Scan, and BIST architectures
Proficiency with ATPG and EDA tools like TestMax, Tetramax, Tessent
Gate level simulation debugging using VCS
Nice-to-have
Post-silicon validation and debug experience
Ability to work with ATE patterns and P1687
Scripting skills in Tcl, Python, or Perl
System Verilog Logic Equivalency checking skills
Strong verbal communication in multifaceted environments