Lead Analog Design Engineer

Cadence

Shanghai, China
10+ years high-speed cmos serdes design experience
Advanced cmos technologies 7nm or below
Data rates of at least 10gb/s
This role involves designing and characterizing high-speed transceiver elements such as TIAs, limiting amplifiers, and SerDes/CDR/PLL building blocks at data rates of 10Gb/s and above

Job Summary

  • This role involves designing and characterizing high-speed transceiver elements such as TIAs, limiting amplifiers, and SerDes/CDR/PLL building blocks at data rates of 10Gb/s and above.
  • The ideal candidate will work as a hands-on self-starter to develop design specifications based on input from colleagues, customers, and industry standards.
  • Candidates must have substantial development and business impact by providing analog expertise across multiple projects while guiding junior and middle-level engineers.

Matching Summary

This role involves designing and characterizing high-speed transceiver elements such as TIAs, limiting amplifiers, and SerDes/CDR/PLL building blocks at data rates of 10Gb/s and above.

Skills & Requirements

Must-have

  • 10+ years high-speed CMOS SerDes design experience
  • Advanced CMOS technologies 7nm or below
  • Data rates of at least 10Gb/s
  • Proficient with Cadence design environment
  • Mixed-signal simulation ADE and AMS
  • High-speed layout considerations parasitics crosstalk

Nice-to-have

  • Ph.D. in Electrical Engineering preferred
  • HFSS experience for electromagnetic structures
  • Experience with precision analog circuits
  • Knowledge of multiple industry standards like USB PCIe
  • Hands-on self-starter with strong communication skills

Key Requirements

  • M.S. in Electrical Engineering required
  • 10+ years working/research experience in high-speed CMOS
  • Experience designing in 7nm or below advanced CMOS technologies

Work Rights

Not specified

Tailored Resume

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