Alternance - Ingénieur Méthodologie De Vérification Asic/fpga - F/h

THALES

Toulouse, France
Not specified; not specified; benefits: work-life ...
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Vhdl or verilog/systemverilog mastery
Linux environment and scripting skills
Asic/fpga simulation tools expertise
** Thales is seeking an intern for a 3-year position in ASIC/FPGA verification methodology in Toulouse, France. The role requires candidates to have a background in software, electronics, or microelectronics, with specific skills in VHDL/Verilog, Linux, and UVM methodology. **

Job Summary

  • You will integrate into a team of thirty ASIC/FPGA designers to develop a state-of-the-art verification environment.
  • Your mission includes implementing complete digital verification environments based on the UVM methodology and automating test campaigns.
  • Thales offers an inclusive environment with significant investment in R&D across key innovation domains like AI and cybersecurity.

Matching Summary

Match Score: 75

** Thales is seeking an intern for a 3-year position in ASIC/FPGA verification methodology in Toulouse, France. The role requires candidates to have a background in software, electronics, or microelectronics, with specific skills in VHDL/Verilog, Linux, and UVM methodology. **

Salary

Not specified; Not specified; Benefits: Work-life balance, inclusive environment, ESG recognition

Skills & Requirements

Must-have

  • VHDL or Verilog/SystemVerilog mastery
  • Linux environment and scripting skills
  • ASIC/FPGA simulation tools expertise
  • UVM verification methodology knowledge

Nice-to-have

  • Database management experience
  • Web interface implementation skills
  • Rigor and curiosity in engineering
  • Proactive initiative and dynamism

Key Requirements

  • 3-year apprenticeship (alternance) duration
  • Level Bac+5 Engineering School degree
  • Dominant background in Software, Electronics, or Micro-electronics

Work Rights

Not specified

Tailored Resume

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