Applied Ml – Functional Verification Engineer

Cadence Design Systems Inc.

Base: $114,800 to $213,200 (california); bonus/equ...
3+ years pre-silicon asic verification experience
Expertise in formal, sv/uvm, or ovm methodologies
Proficiency with eda tools like jasper, xcelium, imc
This role involves contributing to the world's first agentic AI platform that autonomously designs and verifies chips with up to 10x productivity gains

Job Summary

  • This role involves contributing to the world's first agentic AI platform that autonomously designs and verifies chips with up to 10x productivity gains.
  • The position requires collaborating closely with machine learning engineers and software engineers to validate output correctness and efficiency.
  • Cadence offers a comprehensive benefits package including paid vacation, 401(k) matching, and opportunities for career development within a diverse team.

Matching Summary

This role involves contributing to the world's first agentic AI platform that autonomously designs and verifies chips with up to 10x productivity gains.

Salary

Base: $114,800 to $213,200 (California); Bonus/Equity: Eligible for incentive compensation; Benefits: Paid vacation, 401(k), medical/dental/vision

Skills & Requirements

Must-have

  • 3+ years pre-silicon ASIC verification experience
  • Expertise in Formal, SV/UVM, or OVM methodologies
  • Proficiency with EDA tools like Jasper, Xcelium, IMC
  • Strong programming skills in Verilog, SystemVerilog, Python
  • Advanced debugging using waveform viewers and simulation analysis

Nice-to-have

  • Exposure to LLMs and ML technologies like RAG, RL
  • Experience with Agentic frameworks for chip design
  • Ability to collaborate with machine learning engineers
  • Proactive approach to continuous learning and innovation

Key Requirements

  • BS degree with 4+ years experience OR MS with 2+ years OR new PhD
  • Minimum 3 years of proven expertise in pre-silicon verification
  • Hands-on experience with industry standard EDA tools

Work Rights

Not specified

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