Job Summary

• Responsible for implementing and extending existing capabilities for circuit and interconnect delay and signal integrity analysis of large scale circuits.
• The role involves designing, tuning, and innovating timing and graph algorithms operating on multi‑billion‑node timing graphs.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Matching Summary

Salary

Base: $101,500 to $188,500; Bonus/Equity: Incentive compensation (bonus, equity); Benefits: Paid vacation, paid holidays, 401(k) plan with employer match, ESPP, medical, dental, vision

Skills & Requirements

Key Requirements

• MS/PhD in EE/CS or related discipline
• Multi-threaded programming experience
• Numerical analysis techniques
• Delay calculation methods for nanometer circuits

Work Rights