Mixed Signal Logic Verification Engineer

Intel

Bangalore, India
Hybrid
System verilog
Uvm
Mix signal ip verification
A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug

Job Summary

  • A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug.
  • Key responsibilities include defining verification plans, guiding junior engineers, improving verification methodologies, ensuring coverage closure, and collaborating with architects for top-level verification.
  • This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Matching Summary

A Senior/Staff VLSI Verification Engineer with 11-15 years of experience drives complex SoC/ASIC verification, focusing on UVM/System Verilog testbench architecture, Mix signal IP verification strategy, and post-silicon debug.

Skills & Requirements

Must-have

  • System Verilog
  • UVM
  • Mix signal IP verification
  • RTL debug
  • gate-level simulations
  • coverage closure

Nice-to-have

  • formal verification
  • Python scripting
  • Perl scripting
  • Tcl scripting
  • mentor junior engineers

Key Requirements

  • 11-15 years of experience in ASIC/SoC verification
  • Expert-level knowledge of System Verilog, UVM, Verilog
  • Proficiency in JTAG/IJTAG/CRI/APB protocols
  • Experience with Synopsys VCS, Cadence Xcelium/JasperGold, Mentor Questa
  • B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering

Work Rights

Not specified

Tailored Resume

Cover Letter