As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing
Job Summary
As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.
Matching Summary
As an STA design engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
Skills & Requirements
Must-have
Static timing analysis
EDA tools like Primetime/PTPX
Interface timing constraints
Timing closure and signoff
Nice-to-have
Communication skills
Problem solving skills
Analytical skills
Key Requirements
3+ Years' experience
BE/MS/Phd in Electronics/Electrical Engineering
Tapeout experience including in latest technology 10nm or lower