Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM
Job Summary
Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world.
Matching Summary
Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
Skills & Requirements
Must-have
UVM verification methodology
PCI Express protocol verification
SystemVerilog expertise
constrained random verification
functional coverage based verification
Nice-to-have
excellent PCIE protocol knowledge
system level architecture understanding
scripting and SW programming skills
debugging and analytical skills
great teammate
Key Requirements
2+ years of relevant experience
B.Tech./ M.Tech or equivalent experience
Experience in verification at Unit/Sub-system/SOC level
Expertise in Verilog and SystemVerilog
Expertise in comprehensive verification of IP or interconnect protocols